The surprising subtleties of zeroing a register (2012)

Author in the old thread (https://news.ycombinator.com/item?id=19262249) says > An x86-64 CPU has sixteen integer registers, but 100-200 physical integer registers. Every time an instruction writes to, say, RAX the renamer chooses an available physical register and does the write to it, recording the fact that RAX is now physical-register #137. This allows the breaking of dependency chains, thus allowing execution parallelism. I'm curious why they have so many more physical registers than... logical? registers. I…

Author here - I just want to drop in to reiterate how awesome register renaming is. It's a bit weird to try and understand, but it is crucial to how these out-of-order processors run, and it is the trick which lets the register zeroing run so efficiently. An x86-64 CPU has sixteen integer registers, but 100-200 physical integer registers. Every time an instruction writes to, say, RAX the renamer chooses an available physical register and does the write to it…

Hey! A word for my friends who are interested in machine architecture, but like me, aren't already experts in the topic. I'd command-clicked this article to read it later, got busy with other stuff, then ran across the tab again. Found it so compelling that I wrote dang - well past midnight! - to see if it could get boosted back to the home page. Turns out this had been done once already, but he gave it another shot thanks…

"You can’t make an xor instruction take, say, 0.6 cycles. But feel free to try." 'Easy': clockless CPUs (http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchrono...)