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RISC-V CPU formal specification F# edition

github.com Software & code Software projects Hardware & electronics Candidate
Screenshot of github.com captured 2026-07-20
Page preview · captured 2026-07-20

Resurfaced independently across 2 calendar years, with breakout response in 2 of them.

submissions
4
submitters
3
observed span
2019–2023
peak thread · 42 comments
134 pts
latest 20+ return · 2023-07-29
134 pts

Submission timeline

2007–2026

One slot for every year since HN launched. Height is that year's peak points; orange marks a 100+ point or 50+ comment breakout. Select a bar to open its strongest thread.

First comments on top threads

HN comment order

RISC-V CPU formal specification written on F#. Formalazation of RISC-V ISA architecture.

To me "formal specification" sounds like it should have some sort of connection to formal methods, i.e., some proof system. This looks more like what I would call an "instruction set simulator". Though if the focus is on clarity and readability rather than performance, "executable specification" might be a good middle ground.

The first top-level comment from each of the four biggest threads, in HN’s own order. Excerpts are shortened; open a comment for full context.

Breakout years
2

100+ points or 50+ comments

Total points
259

reference only — not used in Hall rules or ranking

Total comments
58

reference only — not used in Hall rules or ranking

Every submission

DateTitle as submittedByPointsComments
2019-10-03New open source F# RISC-V ISA formal specification and CPU simulationsfxws200620
2019-10-14F# RISC-V Instruction Set Formal Specificationadamnemecek10
2019-10-20F# RISC-V Instruction Set Formal SpecificationFirst breakoutadamnemecek12216
2023-07-29RISC-V CPU formal specification F# editionBest thread · Latest 20+ point returnmrLSD-dev13442